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functional block diagrams rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a closed-loop high speed buffer buf04* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features bandwidth C 110 mhz slew rate C 3000 v/ m s low offset voltage C <1 mv very low noise C < 4 nv/ ? hz low supply current C 8.5 ma mux wide supply range C 6 5 v to 6 15 v drives capacitive loads pin compatible with buf03 applications instrumentation buffer rf buffer line driver high speed current source op amp output current booster high performance audio high speed ad/da high slew rate and very low noise and thd, coupled with wide input and output dynamic range, make the buf04 an excellent choice for video and high performance audio circuits. the buf04s inherent ability to drive capacitive loads over a wide voltage and temperature range makes it extremely useful for a wide variety of applications in military, industrial, and commercial equipment. the buf04 is specified over the extended industrial (C40 c to +85 c) and military (C55 c to +125 c) temperature range. buf04s are available in plastic and ceramic dip plus so-8 surface mount packages. contact your local sales office for mil-std-883 data sheet and availability. *patent pending. general description the buf04 is a wideband, closed-loop buffer that combines state of the art dynamic performance with excellent dc performance. this combination enables designers to maximize system performance without any speed versus dc accuracy compromises. built on a high speed complementary bipolar (cb) process for better power performance ratio, the buf04 consumes less than 8.5 ma operating from 5 v or 15 v supplies. with a 2000 v/ m s min slew rate, and 100 mhz gain bandwidth product, the buf04 is ideally suited for use in high speed applications where low power dissipation is critical. full 10 v output swing over the extended temperature range along with outstanding ac performance and high loop gain accuracy makes the device useful in high speed data acquisition systems. plastic dip 8-lead and cerdip (p, z suffix) 8-lead narrow-body so (s suffix) buf04 1 2 3 4 8 7 6 5 buf04 null nc in v nc = no connect null out v+ top view 1 1 nc
buf04Cspecifications electrical characteristics parameter symbol conditions min typ max units input characteristics offset voltage v os 0.3 1 mv C40 c t a +85 c 1.3 4 mv input bias current i b v cm = 0 0.7 5 m a C40 c t a +85 c 2.2 10 m a input voltage range v cm 13 v offset voltage drift d v os / d t30 m v/ c offset null range 25 mv output characteristics output voltage swing v o r l = 150 w , 10.5 11.1 v C40 c t a +85 c 10 11 v r l = 2 k w , 13 13.5 v C40 c t a +85 c 13 13.15 v output current C continuous i out 50 65 ma peak output current i outp note 2 80 ma transfer characteristics gain a vcl r l = 2 k w 0.995 0.9985 1.005 v/v C40 c t a +85 c 0.995 0.9980 1.005 v/v gain linearity nl r l = 1 k w , v o = 10 v 0.005 % r l = 150 k w 0.008 % power supply power supply rejection ratio psrr v s = 4.5 v to 18 v 76 93 db C40 c t a +85 c7693 db supply current i sy v o = 0 v, r l = 6.9 8.5 ma C40 c t a +85 c 6.9 8.5 ma dynamic performance slew rate sr r l = 2 k w , c l = 70 pf 2000 3000 v/ m s bandwidth bw C3 db, c l = 20 pf, r l = 110 mhz bandwidth bw C3 db, c l = 20 pf, r l = 1 k w 110 mhz bandwidth bw C3 db, c l = 20 pf, r l = 150 w 110 mhz settling time v in = 10 v step to 0.1% 60 ns differential phase f = 3.58 mhz, r l = 150 w 0.02 degrees f = 4.43 mhz, r l = 150 w 0.03 degrees differential gain f = 3.58 mhz, r l = 150 w 0.014 % f = 4.43 mhz, r l = 150 w 0.008 % input capacitance 3pf noise performance voltage noise density e n f = 1 khz 4 nv/ ? hz current noise density i n f = 1 khz 2 pa/ ? hz note 1 long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 c with an ltpd of 1.3. specifications subject to change without notice. rev. 0 C2C (@ v s = 6 15.0 v, t a = +25 8 c unless otherwise noted)
electrical characteristics parameter symbol conditions min typ max units input characteristics offset voltage v os 0.8 2.0 mv C40 c t a +85 c 1.0 4 mv input bias current i b v cm = 0 v 0.15 5 m a C40 c t a +85 c 1.6 10 m a input voltage range v cm 3.0 v offset voltage drift d v os / d t30 m v/ c offset null range 25 mv output characteristics output voltage swing v o r l = 150 w , 3.0 v C40 c t a +85 c 2.75 3.00 v r l = 2 k w , 3.0 3.6 v C40 c t a +85 c 3.0 3.35 v output current - continuous i out 40 ma peak output current i outp note 2 75 ma transfer characteristics gain a vcl r l = 2 k w , 0.995 0.9977 1.005 v/v C40 c t a +85 c 0.995 1.005 v/v gain linearity nl r l = 1 k w 0.005 % power supply power supply rejection ratio psrr v s = 4.5 v to 18 v 76 93 db C40 c t a +85 c7693 db supply current i sy v o = 0 v, r l = 6.60 8 ma C40 c t a +85 c 6.70 8 ma dynamic performance slew rate sr r l = 2 k w , c l = 70 pf 2000 v/ m s bandwidth bw C3 db, c l = 20 pf, r l = 100 mhz bandwidth bw C3 db, c l = 20 pf, r l = 1 k w 100 mhz bandwidth bw C3 db, c l = 20 pf, r l = 150 w 100 mhz differential phase f = 3.58 mhz, r l = 150 w 0.13 degrees f = 4.43 mhz, r l = 150 w 0.15 degrees differential gain f = 3.58 mhz, r l = 150 w 0.04 % f = 4.43 mhz, r l = 150 w 0.06 % noise performance voltage noise density e n f = 1 khz 4 nv/ ? hz current noise density i n f = 1 khz 2 pa/ ? hz note 1 long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 c, with an ltpd of 1.3. specifications subject to change without notice. (@ v s = 6 5.0 v, t a = +25 8 c unless otherwise noted) buf04 rev. 0 C3C
buf04 rev. 0 C4C wafer test limits parameter symbol conditions limit units offset voltage v os v s = 15 v 1 mv max v os v s = 5 v 2 mv max input bias current i b v cm = 0 v 5 m a max power supply rejection ratio psrr v = 4.5 v to 18 v 76 db output voltage range v o r l = 150 w 10.5 v min supply current i sy v o = 0 v, r l = 2 k w 8.5 ma max gain a vcl v o = 10 v, r l = 2 k w 1 0.005 v/v note electrical tests and wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v maximum power dissipation . . . . . . . . . . . . . . . see figure 16 storage temperature range z package . . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +175 c p, s package . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c operating temperature range buf04z . . . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c buf04s, p . . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c junction temperature range z package . . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c p, s package . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering 60 sec) . . . . . . . . +300 c package type q ja 2 q jc units 8-pin cerdip (z) 148 16 c/w 8-pin plastic dip (p) 103 43 c/w 8-pin soic (s) 158 43 c/w notes 1 absolute maximum ratings apply to both dice and packaged parts, unless otherwise noted. 2 q ja is specified for the worst case conditions, i.e., q ja is specified for device in socket for cerdip, p-dip, and lcc packages; q ja is specified for device soldered in circuit board for soic package. ordering guide temperature package package model range description option buf04az/883 C55 c to +125 c cerdip q-8 buf04gp C40 c to +85 c plastic dip n-8 buf04gs C40 c to +85 c so so-8 buf04gbc +25 c dice dice dice characteristics buf04 die size 0.075 x 0.064 inch, 5,280 sq. mils substrate (die backside) is connected to v+ transistor count 45. (@ v s = 6 15.0 v, t a = +25 8 c unless otherwise noted)
buf04 rev. 0 C5C 0.6 0.0 ?.1 0.5 0.4 0.3 0.2 0.1 offset ?mv 0 units 150 90 30 60 120 0 30 v s = ?5v 315 plastic dips t a = +25? figure 1. input offset voltage (v os ) distribution @ 15 v, p-dip 1.4 0.2 0 1.2 1.0 0.8 0.6 0.4 offset ?mv 125 0 75 25 50 100 units v s = ?v 315 plastic dips t a = +25? figure 2. input offset voltage (v os ) distribution @ 5 v, p-dip 125 ?0 ?5 100 75 50 25 0 ?5 temperature ?? 2.0 ?.0 ?.0 ?.0 ?.0 ?.0 ?.0 0 1.0 offset ?mv ?v ?5v figure 3. input offset voltage (v os ) vs. temperature typical performance characteristicsC 200 0 0.2 120 40 ?.1 80 ?.15 160 0.15 0.1 0.5 0 ?.5 offset ?mv units v s = ?5v 315 cerdips t a = +25? figure 4. input offset voltage (v os ) distribution @ 15 v, cerdip 125 0 1.4 75 25 0.2 50 0 100 1.2 1.0 0.8 0.6 0.4 offset ?mv units v s = ?v 315 cerdips t a = +25? figure 5. input offset voltage (v os ) distribution @ 5 v, cerdip 125 ?0 ?5 100 75 50 25 0 ?5 temperature ?? ?.0 ?.0 ?.0 ?.0 ?.0 ?.0 0 input bias current ?? v s = ?v v s = ?5v figure 6. input bias current vs. temperature
buf04 rev. 0 C6C 125 ?0 ?5 100 75 50 25 0 ?5 temperature ?? 8.0 5.5 7.0 6.0 6.5 7.5 supply current ?ma v s = ?8v v s = ?v v s = ?5v figure 7. supply current vs. temperature 15 ?5 ?2 ?4 ?3 11 ?1 12 13 14 output swing ?volts v s = ?5v r l = 1k r l = 1k r l = 150 125 ?0 ?5 100 75 50 25 0 ?5 temperature ?? r l = 150 r l = 2k r l = 2k w w w w w w figure 8. output voltage swing vs. temperature @ 15 v abs negative swing v s = ?v t a = +25? 10 100 1m 100k 10k 1k load resistance ? w 5 4 0 3 2 1 output swing ?volts positive swing figure 9. maximum v out swing vs. load @ 5 v t a = +25? v s = ?v 1k 10k 100m 10m 1m 100k frequency ?hz 50 25 0 30 35 40 45 5 10 15 20 output impedance ? w v s = ?5v figure 10. output impedance vs. frequency 5.0 ?.0 ?.5 ?.5 ?.0 3.0 ?.0 3.5 4.0 4.5 output swing ?volts v s = ?v r l = 2k , 1k r l = 150 125 ?0 ?5 100 75 50 25 0 ?5 temperature ?? w w r l = 150 w w r l = 2k , 1k w w figure 11. output voltage swing vs. temperature @ 5 v v s = ?5v t a = +25? 10 100 10k 1k load resistance ? w 16 8 0 4 12 14 10 6 2 output swing ?volts positive swing abs negative swing figure 12. maximum v out swing vs. load @ 15 v
buf04 rev. 0 C7C 10 ? ?0 8 6 4 2 0 ? ? ? common mode voltage ?volts 0.5 ?.0 ?.5 ?.5 ?.0 0 input bias current ?? t a = +25? figure 13. bias current vs. input voltage 1k 10k 100m 10m 1m 100k frequency ?hz 100 50 0 60 70 80 90 10 20 30 40 power supply rejection ?db t a = +25? v s = ?, ?5v +psrr ?psrr figure 14. power supply rejection vs. frequency 6000 0 3000 1000 2000 5000 4000 slew rate ?v/? 125 ?0 ?5 100 50 25 0 75 ?5 temperature ?? v s = ?5v +edge ?dge figure 15. slew rate vs. temperature 0 125 25 100 75 50 85 temperature ? c 0 1.5 1.0 0.5 power dissipation ?w t j max = 150? free air no heat sink q ja = 148?/w q ja = 158?/w q ja = 103?/w p dip cerdip soic figure 16. maximum power dissipation vs. ambient temperature 10 0 100 110 1m 100k 10k 1k 100 frequency ?hz input noise voltage spectral density ?nv/ hz figure 17. input noise voltage vs. frequency 250 50 0 200 150 100 capacitive load ?pf 6000 0 3000 1000 2000 5000 4000 slew rate ?v/? positive slew rate negative slew rate v s = ?5v swing = ?0v t a = +25? figure 18. slew rate vs. capacitive loads
buf04 rev. 0 C8C 250 50 0 200 150 100 capacitance ?pf 150 0 75 25 50 125 100 bandwidth ?mhz phase ?deg ?5 ?80 ?12.5 ?57.5 ?35 ?7.5 ?0 t a = +25? v s = ?v phase @ r l = 150 phase @ r l = 2k bandwidth w w figure 19. bandwidth and phase vs. capacitive loads @ 5 v ?5 ?0 ? supply voltage ?olts 140 80 110 90 100 130 120 bandwidth ?mhz r l = 2k w ?5? +25? +125? figure 20. bandwidth vs. supply voltage and temperature 10 ? ?0 8 4 2 0 6 ? ? ? output voltage ?volts 1.5 ?.5 0 ?.0 ?.5 1.0 0.5 gain deviation ?db 6 ? 0 ? ? 4 2 phase deviation ?degrees phase gain v s = ?5v v in = 0.1v rms frequency = 10mhz r l = 150 w figure 21. gain and phase deviation, r l = 150 w 250 50 0 200 150 100 capacitance ?pf 150 0 75 25 50 125 100 bandwidth ?mhz phase ?deg ?5 ?80 ?12.5 ?57.5 ?35 ?7.5 ?0 t a = +25? v s = ?5v r l = 150 r l = 2k bandwidth phase w w figure 22. bandwidth & phase vs. capacitive loads @ 15 v 100 1k 10k resistive load ? w 200 100 0 50 150 bandwidth ?mhz t a = +25? v s = ?5v figure 23. bandwidth vs. loads 10 ? ?0 8 4 2 0 6 ? ? ? output voltage ?volts 0.075 ?.075 0 ?.050 ?.025 0.050 0.025 gain deviation ?db phase gain v s = ?5v v in = 0.1v rms frequency = 10mhz r l = 2k phase deviation ?degrees ?.5 0 ?.0 ?.5 1.0 0.5 1.5 w figure 24. gain and phase deviation, r l = 2 k w
buf04 rev. 0 C9C functional description the buf04 is a closed-loop voltage buffer based on a current feedback architecture. its high open-loop transimpedance, high output current drive capability, and its low input offset voltage makes it useful in a variety of applications, such as buffering the inputs of sampling and flash a/d converters, audio and video line drivers, active filters, and precision op amp hoosters. a transistor-level equivalent circuit for the buf04 is illustrated in figure 29. the input stage consists of a pair of emitter follower transistors, q1 and q2, whose outputs drive a second set of transistors, q3 and q4. the emitters of q3 and q4 are connected together through diodes, d1 and d2, to form a low impedance input for the feedback signal (in current mode) from the output stage. the outputs of q3 and q4 are then mirrored to q5 and q6 which form the gain stage of the buf04. the signal is taken from the collectors of q5 and q6 which drive a darlington-connected output stage made up of transistors q7-q10. three r-c networks (r1Cc1, r2Cc2, and r3Cc3) form feed-forward paths which bypass certain sections of the buf04 for improved high frequency performance and capacitive load drive capability. since the signal conveyed internally in the buf04 is a current, the frequency response and slew rate of the buf04 are insensitive to supply voltage variations. 12 0 ?2 10k 100k 1000m 100m 10m 1m 3 6 9 ? ? ? gain ?db frequency ?hz v s = ?5v t a = +25 c r l = 150 c l = 100pf c l = 50pf c l = 0pf 150 c l 10 buf04 w w w figure 28. bandwidth vs. frequency q11 q13 q5 q3 q7 q9 q2 q1 c1 c3 r3 d2 d1 q4 r2 q10 q8 q6 q14 q12 v in v out c2 r fb 100 w 20 w 20 w figure 29. transistor-level equivalent circuit an interesting feature of the buf04 architecture is the use of slew-enhancement transistors, q11Cq14. under normal small signal (v in < 2 v be s) conditions, these transistors are normally off. in large signals, high speed transient applications where the input signal is > 2 v be s, these transistors turn on and literally brute-force the output to follow the input. when the input signal drops below 2 v be s, the transistors return to their normally off state. 10 100 0% 90 50mv 10ns 50mv input (50mv/div) output (50mv/div) v s = ?5v, r l = 2k w , c l = 15pf figure 25. small-signal transient response 10 100 0% 90 2v 50ns 2v input (2v/div) output (2v/div) v s = ?5v, r l = 2k w , c l = 15pf dly 375.0ns figure 26. large-signal transient response 0.1 0.010 0.001 0.0001 20 100 1k 10k 20k 07 mar 93 21:31:53 audio precision buf04 thd+n (%) vs freq (hz) t a d b c v s = ?5v lpf=80khz : v in = 0.775v rms, r l = 150w : v in = 0.775v rms, r l = 600w a : v in = 7.75v rms, r l = 150w b : v in = 7.75v rms, r l = 600w a b c d c c d figure 27. thd + noise vs. amplitude
buf04 rev. 0 C10C a two-terminal equivalent circuit of the buf04 is shown in figure 30 where the transistor-level equivalent circuit is reduced to its essential elements. the input stage develops a signal current, i in , that is replicated by an internal current conveyor so as to flow through r t , the transimpedance of the buf04. the voltage developed across r t is buffered by a unity-gain output voltage follower. with an open-loop r t of 400 k w and an r in of 30 w , the voltage gain of the buf04, given by the ratio r t /r in is approximately 13,000accurate to approximately 13.5 bits. the buf04s open-loop ac transimpedance response is determined by the open-loop pole formed by r t and c t . since c t is typically 8 pf, the open-loop pole occurs at approximately 50 khz. x1 i in r t r in i in v out c t v in xi r fb r in = 30 r t = 400 k c t = 8pf rfb = 100 w w w figure 30. current-feedback functional equivalent circuit of the buf04 grounding and bypassing considerations to take full advantage of the buf04s very wide bandwidth, high slew rates, and dynamic range capabilities requires due diligence with regard to supply bypassing. in high speed circuits, the supply bypassing network must provide a very low impedance return path for currents flowing to and from the load network. as with any high speed application, multiple bypassing is always recommended. a 10 m f tantalum electrolytic in parallel with a 0.1 m f ceramic capacitor is sufficient for most applications. for those high speed applications where output load currents approach 50 ma, small valued resistors (1.1 w to 4.7 w ) in series with the tantalum capacitors may improve circuit transient response by damping out the capacitors self- inductance. figure 31 illustrates bypassing recommendations. buf04 7 6 10? r1 0.1? v+ 0.1? v 10? r2 4 3 r s r l kelvin return for load current kelvin return for load current v in v out note use short lead lengths (<5mm) figure 31. recommended power-supply bypassing to minimize the effects of high-frequency coupling, circuits must be built with short interconnect leads, and large ground planes should he used whenever possible to provide a low resistance, low-inductance circuit path. sockets should be avoided because the increased interlead capacitance can degrade bandwidth and stability. if sockets are necessary, individual pin sockets (oftentimes called cage jacks, amp part no. 5-330808-3 or 5-330808-6) should be used. they contribute far less stray reactance than molded socket assemblies. offset voltage nulling although the offset voltage of the buf04 is very low (1 mv, maximum) for such a high speed buffer, the circuit shown in figure 32 can be used if additional offset voltage nulling is required. a potentiometer ranging from 1 k to 10 k can be used for v os nulling; with a 10 k w potentiometer, the trim range is 30 mv. v+ buf04 7 6 10? 0.1? 0.1? v 10? 4 3 v in 10k 1 v out trim range ?0mv 8 figure 32. optional offset voltage nulling scheme applications output short-circuit protection to optimize the transient response and output voltage swing of the buf04, internal output short-circuit current limiting was omitted. although the buf04 can provide continuous output currents of 50 ma without protection, direct connection of the buf04s output to ground or to the supplies will destroy the device. an active current limit technique, illustrated in figure 33, provides the necessary short-circuit protection while retaining full dc output voltage swing to the load. buf04 7 6 10? 0.1? 0.1? ?5v 10? 4 3 v in v out +15v rsc2 3 10 w 2n2219 2n2219 2n2905 2n2905 rsc1 3 10 w 0.01? set isc +(isc? <60ma, continuous rsc1 (rsc2) = 0.6v isc + (isc? 6.2k w figure 33. short-circuit current limiting using current sources
buf04 rev. 0 C11C output current transient recovery settling characteristics of high speed buffers also include the buffers ability to recover, i.e., settle, from a transient output current load condition. when driving the input of an a/d converter, especially the successive-approximation converter types, the buffer must maintain a constant output voltage under dynamically changing load current conditions. in these types of converters, the comparison point is usually diode-clamped, but it may deviate several hundred millivolts resulting in high frequency modulation of the a/d input current. open-loop and closed-loop buffers (also, op amps configured as followers) that exhibit high closed-loop output impedances and/or low unity gain crossover frequencies recover very slowly from output load current transients. this slow recovery leads to linearity errors or missing codes because of errors in the instantaneous input volt- age. therefore, the buffer (or op amp) chosen for this type of application should exhibit low output impedance and high unity gain bandwidth so that its output has had a chance to settle to its nominal value before the converter makes its comparison. the circuit in figure 34 illustrates a settling measurement circuit for evaluating the recovery time of high speed buffers from an output load current transient. the input to the buffer is grounded for ease of measuring the recovery time, and two resistors are used to sum steady-state and transient load currents at the output. as a worst-case condition, r1, was chosen such that the buf04 would source (or sink) a steady-state current of 25 ma. r2 was then chosen to add a 10 ma transient current upon the steady-state value. to set accurately the nodal voltages internal to the buf04, the supply voltages were offset by the voltage applied to r1. because of its high transimpedance, wide bandwidth, and low output impedance, the buf04 exhibits an extremely fast recovery time of 60 ns to 0.01%, as shown in figure 34. results were identical regardless whether the buf04 was sourcing or sinking current. buf04 7 6 0.1? 0.1? 10? 4 3 tp2 tp1 r2 250 w 10? r1 200 w v load v+ source: ?v sink: +5v v in source: 0 ? ?.5 v sink: 0 ? +2.5v v figure 34. transient output load current test circuit 10 90 100 0% 5mv 59.00ns 20ns 100mv d t i source (4ma/div) v out (5mv/div) 35ma 25ma figure 35. buf04s output load current recovery time terminated line drivers the buf04s high output current, large slew rate, and wide bandwidth all combine to make it an ideal device for high speed line driver applications. as shown in figure 36, the buf04 can be configured for driving doubly terminated 50 w and 75 w cables. to optimize the circuits pulse response, a capacitor, c t (c x + c trim ), is connected across the series back termination. the buf04 can drive a 50 w line to 2.5 v and a 75 w line to 3.75 v when operating on 15 v supplies. 6 3 v in 6' coax r l buf04 r s r x c t c x z o 50 w 75 w coax rg-58 rg-59 r s , r l 50 w 75 w r x 50 75 c x 91pf 62pf c t 3?5pf 3?5pf figure 36. line driver configuration low-pass active filter in many signal-conditioning applications, filters are required to band-limit noise or altogether eliminate other unwanted signals prior to conversion. often, high frequency filters are needed for these applications; however, there are few op amps that exhibit the high open-loop gain and wide unity-gain crossover frequency required for these applications. as illustrated in figure 37, the buf04 and a handful of passive components can be configured as a high frequency, low-pass active filter. since the filter configuration is a unity-gain sallen-key topology, the buf04 is particularly well suited for this application. in this circuit, an additional resistor, r3, was added to prevent interaction between c2 and the buf04s input capacitance. buf04 6 3 v in v out r1 499 w r2 499 w r3 47 w c1* 44pf (22pf x 2) c2* 22pf * silvered mica or dipped ceramic w o = r1 ? r2 ? c1 ? c2 1 ; q = 4 ?c2 c1 figure 37. a 10 mhz low-pass active filter
buf04 rev. 0 C12C operation within an op amp feedback loop the buf04 is well suited as a current booster or isolation buffer within the closed loop of precision op amps such as the op177, the op97, the op27, or the op77. since the buf04 is a closed loop voltage buffer, no interstage coupling resistor between the op amp and the buffers input is required for circuit stability. the wide bandwidth and high slew rate of the buf04 assure that the loop has the characteristics of the op amp; hence, no additional rolloff is required. buf04 6 3 r l 500 w op177 v in 3 r2 r1 100 2 c l 1000pf 6 gain 10 100 1000 r2 (k w ) 1 10 100 v out figure 38. buf04 as booster stage for a precision op amp paralleling buf04s for increased load drive capability in applications where continuous output currents greater than 50 ma are required or where heat management is an issue, a number of buf04s can be connected in parallel to reduce the drive requirement of any one buffer. an example of one such application is illustrated in figure 39. in this circuit, the buf04s are required to drive a doubly terminated 50 w line to 5 v. this type of a load for a single buf04 would certainly cause a power dissipation problem. parallel operation results in lower input and output impedances and increased bias currents; on the other hand, input equivalent noise voltage is reduced and input offset voltage remains unchanged. v in ?0v r l 50 w v out 3 r3 100 w r1 47 w 6 buf04 r s 50 w 3 r2 47 w 6 buf04 ?v r4 100 w figure 39. paralleling buf04s for high output currents overdrive recovery and phase reversal in applications where the inputs could be driven to the supply rails, the buf04 recovers in 10 ns from positive or negative overdrive. the buf04 does not exhibit any output voltage phase reversal when the input signal exceeds its input voltage range.
buf04 rev. 0 C13C * buf04 spice macro-model 7/93, rev. a * jcb / pmi * * copyright 1993 by analog devices, inc. * * * node assignments * noninverting input * positive supply * negative supply * output * * .subckt buf04 1 99 50 6 * * input stage * r1 99 8 200 r2 10 50 200 v1 99 9 4.4 d198dx v2 11 50 4.4 d2 10 11 dx i1 99 5 1.8e-3 i2 4 50 1.8e-3 q1 50 3 5 qp q2 99 3 4 qn q3 8 61 30 qn q4 10 7 30 qp r3 5 61 50e3 r4 4 7 50e3 cp1 61 99 14e-15 cp2 7 50 14e-15 rfb 6 2 100 * * input error sources * ib1 99 1 0.7e-6 vos 3 1 0.7e-6 ls1 30 2 1e-9 cs1 99 2 2.0e-12 cs2 99 1 3.0e-12 * eref 97 0 22 0 1 * * transconductance stage * r5 12 97 365e3 c3 12 97 8e-12 g1 97 12 99 8 se-3 g2 12 97 10 50 se-3 e3 13 97 poly(1) 99 97 C2.5 1.1 e4 97 14 poly(1) 97 50 C2.5 1.1 d3 12 13 dx d4 14 12 dx r6 12 15 200 c2 15 6 20e-12 * * pole at 200 mhz * r11 20 97 1e6 c7 20 97 0.759e-15 g7 97 20 12 22 1e-6 * * pole at 200 mhz * r12 21 97 1e6 c8 21 97 0.759e-15 g8 97 21 20 22 1e-6 * * outpu t stage * fsy 99 50 poly(2) v7 v8 1.85e-3 1 1 r13 22 99 16.67e3 r14 22 50 16.67e3 r15 27 99 80 r16 27 50 80 l2 27 6 10e-9 g11 27 99 99 21 12.5e-3 g12 50 27 21 50 12.5e-3 v5 23 27 3.3 v6 27 24 3.3 d5 21 23 dx d6 24 21 dx g10 97 70 27 21 12.5e-3 d7 70 71 dx d8 72 70 dx v7 71 97 dc 0 v8 97 72 dc 0 * * models used * .model qn npn(bf= 1000 is= 1e-15) .model qp pnp(bf= 1000 is= 1e-15) .model dx d(is= 1e-15) .ends buf04
buf04 rev. 0 C14C buf04 spice d3 g1 g2 r5 97 12 c3 e3 d4 e4 14 13 r6 15 c2 6 g7 r11 c7 g8 r12 c8 21 20 97 v7 d7 71 v8 d8 72 g10 97 fsy r13 22 r14 99 50 g11 r15 r16 g12 23 24 d5 d6 21 v5 v6 27 l2 6 70 cs2 +in ib1 99 v os 50 1 3 q2 i2 r4 7 5 r3 61 cp2 r2 v2 d2 11 30 ls1 cs1 v1 d1 2 6 rfb r1 q3 q4 cp1 i1 q1 10 8 4 9 12
buf04 rev. 0 C15C outline dimensions dimensions shown in inches and (mm). 8-lead plastic dip (n-8) pin 1 0.280 (7.11) 0.240 (6.10) 4 5 8 1 seating plane 0.015 (0.381) typ 0.130 (3.30) min 0.210 (5.33) max 0.160 (4.06) 0.115 (2.93) 0.430 (10.92) 0.348 (8.84) 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-lead cerdip (q-8) 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 15 0 0.005 (0.13) min 0.055 (1.4) max 1 pin 1 4 5 8 0.310 (7.87) 0.220 (5.59) 0.405 (10.29) max 0.200 (5.08) max seating plane 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 8-lead narrow-body so (r-8) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 pin 1 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 4 5 1 8 0.102 (2.59) 0.094 (2.39) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0040 (0.10) 0.1968 (5.00) 0.1890 (4.80)
buf04 rev. 0 C16C c1856C10C10/93 printed in u.s.a.

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